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10/21/ 10/21/ 19-5075; 12/09 1 of 23 features ? 1024 bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit crc tester) assures absolute traceability be cause no two parts are alike ? built-in multidrop controller ensures compatibility with other microlan products ? eprom partitioned into four 256-bit pages for randomly accessing packetized data ? each memory page can be permanently write-protected to prevent tampering ? device is an ?add onl y? memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by superseding an old page in favor of a newly programmed page ? reduces control, address, data, power, and programming signals to a single data pin ? directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kbits per second ? 8-bit family code specifies ds2502 communications requirements to reader ? presence detector acknowledges when the reader first applies voltage ? low cost to-92 or 8-pin so, sot-23 (3- pin), tsoc and flip chip surface mount package ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to +50c ds2502 1kb add-only memory www.maxim-ic.com pin assignment 12 0 9rr d flip chip, top view with laser mark, contacts not visible. ?rrd? = revision/date 1 = data 2 = gnd see 21-0250 for package outline. note: the leads of to-92 packages on tape- and-reel are formed to approximately 100 mil (2.54 mm) spacing. for details refer to drawing 21-0250 . data 1 2 3 6 5 4 top v iew tsoc package gnd n c nc nc nc 1 to-9 2 2 3 4 8 7 6 5 nc nc nc nc nc nc ds2502 data gnd 8-pin so (150 mil) gnd data nc sot-23 package top view 1 2 3 09rr 1 2 3 1 = data; 2, 3 = gnd bottom view ?rr ? = revision
ds2502 2 of 23 ordering information standard lead-free description ds2502 ds2502+ to-92 package ds2502/t&r ds2502+t&r to-92 package, 2k tape & reel ds2502r/t&r ds2502r+t&r 3-pin sot-23 package, 3k tape & reel ds2502p ds2502p+ 6-pin tsoc package ds2502p/t&r ds2502p+t&r tsoc package, 4k tape & reel ds2502s ds2502s+ 8-pin so package ds2502s/t&r ds2502s+t&r so package, 2.5k tape & reel ds2502x1 flip chip, 10k tape & reel + indicates lead-free compliance. description the ds2502 1kb add-only memory identifies and stor es relevant informati on about the product to which it is associated. this lot- or product-specific information can be accessed with minimal interface- for example, a single port pin of a microcontroller. th e ds2502 consists of a f actory-lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (09h) plus 1kb of eprom which is user-pro grammable. the power to program and read the ds2502 is derived entirely from the 1-wire ? communication line. data is transferred serially via the 1-wire protocol which requires only a single data lead and a ground return. the entire device can be programmed and then write-protected if desire d. alternatively, the part may be programmed multiple times with new data be ing appended to, but not overwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provi sion is also included for indicating that a certain page or pages of data are no longer va lid and have been replaced with new or updated data that is now residing at an alternate page address. th is page address redirection allows software to patch data and enhance the flexibility of the device as a stand-alone database. the 48-bit serial number that is factory-lasered into each ds2502 provides a guarant eed unique identity which allows for absolute traceability. the familiar to-92 or soic or tsoc packages provide a compact enclosure that allows standard assembly equipment to handle the device eas ily for attachment to printed circuit boards or wiring. typical applications include storage of calibration constants, maintenance records, asset tracking, product revision status, and access codes. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2502. the ds2502 has three main data component s: 1) 64-bit lasered rom, 2) 1024-bit eprom, and 3) eprom status bytes. the de vice derives its power for read oper ations entirely from the 1-wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to ope rate off of this ?parasite? power sour ce during the low times of the 1-wire line until it returns high to replenish the para site (capacitor) supply. during programming, 1-wire communication occurs at normal vo ltage levels and then is pulse d momentarily to the programming voltage to cause the selected eprom bits to be programmed. the 1-wire line must be able to provide 12 volts and 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltages are present on the 1-wire line a special high voltage dete ct circuit within the ds2502 generates an internal logic signal to indicate th is condition. the hierarchical structure of the 1- wire protocol is shown in figure 2. the bus master must first pr ovide one of the six rom function commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64-bit lasered rom portion of e ach device and can singulate a speci fic device if many are present on
ds2502 the 1-wire line as well as indicate to the bus master how many and what types of devices are present. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory func tions that operate on the eprom portions of the ds2502 become accessible and the bus master may issue any one of the five memory function commands specific to the ds2502 to read or program the various data fields. the protocol for these memory function commands is described in figure 5. al l data is read and writ ten least significant bit first. 64-bit lasered rom each ds2502 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3). the 64-bit rom and rom function cont rol section allow the ds2502 to ope rate as a 1-wire device and follow the 1-wire protocol detailed in the section ?1-wire bus system.? the memory functions required to read and program the eprom sections of th e ds2502 are not accessible until the rom function protocol has been satisfied. this pr otocol is described in the rom functions flow chart (figure 9). the 1- wire bus master must first provide one of four ro m function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom f unction sequence has been successfully executed, the bus master may then provide any one of the memo ry function commands speci fic to the ds2502 (figure 6). the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. figure 4 shows a hardware implementation of this crc generator. additional information about the dallas semiconductor 1-wire cyclic redundancy check is available in application note 27 . the shift register acting as the crc accumulator is initiali zed to 0. then starting with the l east significant bit of the family code, 1 bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been en tered, the shift register contains the crc value. shifting in the 8 bits of crc shoul d return the shift register to all 0s. ds2502 block diagram figure 1 parasite power data 1-wire bus 64-bit lasered rom 1-wire function control program voltage detect memory function control 8-bit scratchpad 8-bit crc generator 1024-bit eprom (4 pages of 32 bytes) status bytes eprom 3 of 23
ds2502 hierarchical structure for 1-wire protocol figure 2 64-bit lasered rom figure 3 8?bit crc code 48?bit serial number 8?bit family code (09h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 4 of 23
ds2502 5 of 23 1024-bits eprom the memory map in figure 5 shows the 1024-bit epro m section of the ds2502 which is configured as four pages of 32 bytes each. the 8- bit scratchpad is an additional register that acts as a buffer when programming the memory. data is first written to th e scratchpad and then veri fied by reading an 8-bit crc from the ds2502 that confirms pr oper receipt of the data. if th e buffer contents are correct, a programming voltage should be applied and the byte of data will be written into the selected address in memory. this process ensures data integrity when programming the memory. the details for reading and programming the 1024-bit eprom portion of the ds2502 are given in the memory function commands section. eprom status bytes in addition to the 1024 bits of da ta memory the ds2502 provides 64 bits of status memory accessible with separate commands. the eprom status bytes can be r ead or programmed to indicate vari ous conditions to the software interrogating the ds2502. the first byte of the eprom status memo ry contain the write protect page bits which inhibit programming of the corresponding page in the 1024-b it main memory area if the appropriate write protection bit is programmed. once a bit has been programmed in the write protect page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. the next 4 bytes of the eprom status memory c ontain the page address redirection bytes, which indicate if one or more of the pages of data in the 1026-bit eprom section have been invalidated and redirected to the page ad dress contained in the appr opriate redirection byte. th e hardware of the ds2502 makes no decisions based on the contents of the page address redirection bytes. these additional bytes of status eprom technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space permitti ng, an entire page of data can be redirected to another page within the ds2502 by writing the one?s comp lement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the user?s software to ma ke a ?data patch? to the eprom by indicating that a particular page or pages should be replaced with those indicated in th e page address redirection bytes. if a page address redirection byte has an ffh value, the data in the main me mory that corresponds to that page is valid. if a page address redirection by te has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one?s complement of the page address i ndicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, fo r example, would indicate that the updated data is now in page 2. the details for reading and programming the ep rom status memory portion of the ds2502 are given in th e memory function commands section. memory function commands the ?memory function flow chart? (figure 6) de scribes the protocols ne cessary for accessing the various data fields within the ds2502. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpre t the commands issued by the bus master and create the correct control signals within the device. a 3-byte prot ocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two addres s bytes to determine the specific starting byte location within a data field. the command byte indicates if the device is to be read
ds2502 or written. writing data involves no t only issuing the correct comma nd sequence by also providing a 12- volt programming voltage at th e appropriate times. to execute a writ e sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequences always occur a byte at a time. to execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location a nd continuing to the end of the selected data field or until a reset sequence is issued. al l bits transferred to the ds2502 a nd received back by the bus master are sent least significant bit first. ds2502 memory map figure 5 6 of 23
ds2502 memory function flow chart figure 6 7 of 23
ds2502 memory function flow chart figure 6 (cont?d) legend: 8 of 23 decision made by th e master decis ion made byds2502
ds2502 memory function flow chart figure 6 (cont?d) 9 of 23
ds2502 10 of 23 read memory [f0h] the read memory command is used to read data from the 1024-bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) th at indicates a starting byte location within the data field. an 8-bit crc of the comma nd byte and address bytes is computed by the ds2502 and read back by the bus master to confirm that the co rrect command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the ds2502 st arting at the initial addr ess and continuing until the end of the 1024-bit data field is r eached or until a reset pulse is issue d. if reading occurs through the end of memory space, the bus master may issue eight a dditional read time slots and the ds2502 will respond with a 8-bit crc of all data bytes read from the initial starting byte through the last byte of memory. after the crc is received by the bus master, any subsequent read time slots will app ear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching th e end of memory will not have the 8-bit crc available. typically a 16-bit crc would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see application note 114 for the recommended file structure.) if crc values are imbedded within the data, a reset pulse may be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data from the eprom status data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) th at indicates a starting byte location within the data field. an 8-bit crc of the comma nd byte and address bytes is computed by the ds2502 and read back by the bus master to confirm that the co rrect command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the ds2502 st arting at the supplied address and continuing until the end of the eprom status data field is reached. at that point the bus master will receive an 8-bit crc that is the result of shifting into the crc generator all of the data bytes from the initial starting byte through the final factory-programmed byt e that contains the 00h value. this feature is provided since th e eprom status information may change over time making it impossible to program the data once and include an accompanyi ng crc that will always be valid. therefore, the read status command supplies a 8-bit crc that is based on and always is consistent with the current data stored in the eprom status data field. after the 8-bit crc is read, the bus master will receive logical 1s fr om the ds2502 until a reset pulse is issued. the read status command sequence can be ended at any point by issuing a reset pulse. read data/generate 8-bit crc [c3h] the read data/generate 8-bit crc command is used to read data from the 1024- bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8- bit crc of the command byte and address bytes is computed by the ds2502 and read back by th e bus master to confirm that the correct command word and starting address were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc receive d by the bus master is correct, the bus master issues read time slots and receives data fr om the ds2502 starting at the initial address and continuing until the end of a 32-byte page is reached. at that point the bus master will send
ds2502 11 of 23 eight additional read time slots and receive an 8- bit crc that is the result of shifting into the crc generator all of the data bytes from the initial starting byte to the last byte of th e current page. once the 8- bit crc has been received, data is again read from the 1024-bit eprom data fi eld starting at the next page. this sequence will continue until the final page and its ac companying crc are read by the bus master. thus each page of data can be considered to be 33 bytes long: the 32 bytes of user-programmed eprom data and an 8-bit crc that gets genera ted automatically at the end of each page. this type of read differs from the read memory co mmand which simple reads each page until the end of address space is reached. the read memory command only generates an 8-bit crc at the end of memory space that often might be ignored, since in many applications the user would store a 16-bit crc with the data itself in each page of the 1024-bit eprom data field at the time the page was programmed. the read data/generate 8-bit crc command provides and alternate read capability for applications that are ?bit-oriented? rather than ?page-oriented? wh ere the 1024-bit eprom info rmation may change over time within a page boundary ma king it impossible to program the page once and include an accompanying crc that will always be valid. theref ore, the read data/generate 8-bit crc command concludes each page with the ds2502 generating and supplying an 8-bit crc that is based on and therefore is always consistent with the current data stored in each page of the 1024-bit eprom data field. after the 8-bit crc of the last page is read, the bus master will rece ive logical 1s from the ds2502 until a reset pulse is issued. the read data/generate 8-bit crc command sequence can be exited at any point by issuing a reset pulse. write memory [0fh] the write memory command is used to program th e 1024?bit eprom data field. the bus master will follow the command byte with a 2-by te starting address (ta1=(t7:t0), ta2=(t5:t8)) and a byte of data (d7:d0). an 8-bit crc of the command byte, addre ss bytes, and data byte is computed by the ds2502 and read back by the bus master to confirm that th e correct command word, st arting address, and data byte were received. the highest starting address within the ds2502 is 007fh. if the bus master sends a starting address higher than this, the nine 9 most significant address bits are set to 0 by the intern al circuitry of the chip. this will result in a mismatch between the crc cal culated by the ds2502 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a rese t pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 s) is issued by the bus master. prior to programming, the entire unprogrammed 1024- bit eprom data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 1024-bit eprom will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 s programming pulse is applied and the da ta line returns to a 5-vo lt level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the ds2502 responds with the data from the selected eprom address sent least significant bit fi rst. this byte contains the logical and of all bytes written to this eprom data addre ss. if the eprom data byte contains 1s in bit positions where the byte issued by the master contains 0s, a re set pulse should be issued and the current byte address should be programmed again. if the ds2502 eprom data byt e contains 0s in the same bit positions as the data byte, the programm ing was successful and the ds2502 will automatically increment its address counter to select the next byte in the 1024-bit eprom data field. the least
ds2502 12 of 23 significant byte of the new two-byte address will also be loaded into the 8-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2502 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the lsb of the current address; the result is an 8-bit crc of the new data byte and the lsb of the new address. after supplying th e data byte, the bus master will read this 8-bit crc from the ds2502 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset puls e must be issued and the write memory command sequence must be restarted. if th e crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through th e write memory flow chart will ge nerate an 8-bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write memory flow chart due to the ds2502 automatically incrementing its address counter will gene rate an 8-bit crc that is the result of loading (not shifting) the lsb of the new (incremented) addr ess into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2502) is made entirely by the bus master, since the ds2502 will not be able to determine if the 8-bit crc calculated by the bus master agrees wi th the 8-bit crc calculated by the ds2502. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorre ct programming could occur within the ds2502. also note that the ds2502 will always increment its internal address counter after the re ceipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master, therefore if the eprom data byte does not match the supplied data byte does not match the suppli ed data byte but the master but th e master continues with the write memory command, incorrect programming could occur within the ds2502. the write memory command sequence can be exited at a ny point by issuing a reset pulse. write status [55h] the write status command is used to program the ep rom status data field. th e bus master will follow the command byte with a 2-byte star ting address (ta1=(t7:t0), ta2=(t15: t8)) and a byte of status data (d7:d0). an 8-bit crc of the command byte, addre ss bytes, and data byte is computed by the ds2502 and read back by the bus master to confirm that th e correct command word, st arting address, and data byte were received. if the crc read by the bus master is incorrect, a rese t pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, a programmi ng pulse (12 volts on the 1- wire bus for 480 s) is issued by the bus master. prior to programming, the first 7 bytes of the eprom status data field will appear as logi cal 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the select ed byte of the eprom status data field will be programmed to a logical 0 after th e programming pulse has been appl ied at the byte location. the 8th byte of the eprom status byte data fi eld is factory-programmed to contain 00h. after the 480 s programming pulse is applied and the da ta line returns to a 5-vo lt level, the bus master issues eight read time slots to verify that th e appropriate bits have been programmed. the ds2502 responds with the data from the selected eprom status address sent least signif icant bit first. this byte contains the logical and of all bytes written to this eprom status by te address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the ds2502 eprom status byte
ds2502 13 of 23 contains 0s in the same bit positions as the data byte, the programming was successful and the ds2502 will automatically increment its address counter to sele ct the next byte in the eprom status data field. the least significant byte of the new 2-byte address will also be loaded into the 8-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2502 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the lsb of the current address and the resu lt is an 8-bit crc of the new data byte and the lsb of the new address. after supplying th e data byte, the bus master will read this 8-bit crc from the ds2502 with eight read time slots to confirm that the address incremented properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write status command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write status flow chart will generate an 8-bit crc value that is the result of shifting the command byte into the crc genera tor, followed by the 2 a ddress bytes, and finally the data byte. subsequent passes through the write status flow char t due to the ds2502 automatically incrementing its address counter will generate an 8-bit crc that is the re sult of loading (not shifting) the lsb of the new (incremented) addre ss into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2502) is made entirely by the bus master, since the ds2502 will not be able to determine if the 8-bit crc calculated by the bus master agrees wi th the 8-bit crc calculated by the ds2502. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorre ct programming could occur within the ds2502. also note that the ds2502 will always increment its internal address counter after the re ceipt of the eight read time slots used to confirm the programming of the selected eprom byte. the decision to continue is again made entirely by the bus master, therefore if the eprom data byte does not match the supplied data byte but the master contin ues with the write status command, incorrect programming could occur within the ds2502. the write status command sequence can be ended at any point by issuing a reset pulse. 1-wire bus system the 1-wire bus is a system which has a single bus ma ster and one or more slaves. in all instances, the ds2502 is a slave device. the bus ma ster is typically a microcontrolle r. the discussion of this bus system is broken down into three topics: hardware conf iguration, transaction sequence, and 1-wire signaling (signal type and timing). a 1-wire protocol defines bus transa ctions in terms of the bus state during specified time slots that are initiated on the falling ed ge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each de vice attached to the 1-wire bus must have an open drain connection or three-state outputs. the ds2502 is an open drain part with an internal circuit equivalent to that shown in figure 7. the bus master can be the same equivalent ci rcuit. if a bi-directional pin is not available, sepa rate output and input pins can be tied together. the bus master requires a pullup re sistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figures 8a and 8b. the value of the pullup resistor should be approximately 5 k ? for short line lengths.
ds2502 14 of 23 a multidrop bus consists of a 1-wire bus with multiple slaves attached. at regular speed the 1-wire bus has a maximum data rate of 16.3 kbits per second. if the bus master is also required to perform programming of the eprom portions of the ds2502, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 s is required. the id le state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. transaction sequence the sequence for accessing the ds2502 via the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the ds2502 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the six ro m function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [33h] this command allows the bus master to read th e ds2502?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can be used onl y if there is a single ds2502 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds2502 on a multidrop bus. only the ds2502 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
ds2502 ds2502 equivalent circuit figure 7 bus master circuit figure 8 15 of 23
ds2502 rom functions flow chart figure 9 16 of 23
ds2502 17 of 23 skip rom [cch] this command can save time in a single-drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip ro m command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search ro m command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus . the rom search process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus ma ster performs this simple, three-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes ma y be identified by a dditional passes. see application note 187 for a comprehensive discussion of a rom search, including an actual example. 1-wire signaling the ds2502 requires strict protocols to ensure data integrity. the protocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and program pulse. all these signals except pres ence pulse are initiated by the bus master. the initialization sequence required to begin any communication with th e ds2502 is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds2502 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus ma ster then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds2502 waits (t pdh , 15-60 s) and then transmits the presence pulse (t pdl , 60-240 s). read/write time slots the definitions of write and read time slots are illust rated in figure 11. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2502 to the master by triggering a delay circuit in the ds2502. during write time slots, the delay circuit determines when the ds2502 will sample the data line. for a read data time sl ot, if a ?0? is to be tr ansmitted, the delay circuit determines how long the ds2502 will hold the data line low overriding the ?1? generated by the master. if the data bit is a 1, the device will le ave the read data time slot unchanged. program pulse to copy data from the 8-bit scra tchpad to the 1024-bit eprom memo ry or status memory, a program pulse of 12 volts is applied to the data line after the bus master has confirmed that the crc for the current byte is correct. during progr amming, the bus master controls the tr ansition from a state where the data line is idling high via the pullup resi stor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the ds2502. this programming voltage (figure 12) should be applied for 480 s, after which the bus master return s the data line to an idle high state controlled by the pullup resistor. note that due to the high-voltage programming requirements for any 1-wire eprom device, it is not possible to multidrop non-eprom based 1-wire devices with the ds2502 during programming. an internal diode w ithin the non-eprom based 1-wire devices will attempt to clamp the data line at approximately 8 volts and could potentiall y damage these devices.
ds2502 crc generation the ds2502 has an 8-bit crc stored in the most significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bi t rom and compare it to the value stored within the ds2502 to determine if the rom data has been rece ived error-free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 +1. under certain conditions, the ds2502 also generate s an 8-bit crc value using the same polynomial function shown above and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the ds2502. the memory functio n flow chart of figure 6 indicates that the ds2502 comput es an 8-bit crc for the command, a ddress, and data bytes received for the write memory and the write status commands and then outputs this value to the bus master to confirm proper transfer. similarly the ds2502 com putes an 8-bit crc for the command and address bytes received from the bus master for the read me mory, read status, and read data/generate 8-bit crc commands to confirm that these bytes have been received correctly. the crc generator on the ds2502 is also used to provide verification of error-fr ee data transfer as each page of data from the 1024- bit eprom is sent to the bus master during a read data/generate 8-bit crc command, and for the 8 bytes of information in the status memory field. in each case where a crc is used fo r data transfer validation, the bu s master must calculate a crc value using the polynomial function given above and compar e the calculated value to either the 8-bit crc value stored in the 64-bit rom portion of the ds2502 (for rom reads) or the 8-bit crc value computed within the ds2502. the comparison of crc values a nd decision to continue with an operation are determined entirely by the bus master. there is no circuitry on the ds2502 th at prevents a command sequence from proceeding if the crc stored in or calculated by the ds2502 does not match the value generated by the bus master. proper use of the crc as outlined in the fl ow chart of figur e 6 can result in a communication channel with a very high level of in tegrity. for more details on generating crc values including example implementations in both hardware and software, see application note 27 . initialization procedure ?r eset and prese nce pulses? figure 10 resistor 18 of 23 ma ster ds2502 480s t rstl < 960s 480s t rsth < (includes recovery time) 15s t pdh < 60s 60s t pdl < 240s
ds2502 read/write timing diagram figure 11 write-one time slot ds2502 sampling window 60 ? s ? t slot < 120 ? s 1 ? s ? t low1 < 15 ? s 1 ? s ? t rec < ? write-zero time slot 19 of 23 60 ? s ? t low0 < t slot < 120 ? s 1 ? s ? t rec < ? read-data time slot ds2502 sampling window 60 ? s ? t slot < 120 ? s 1 ? s ? t lowr < 15 ? s resistor 0 ? t release < 45 ? s master 1 ? s ? t rec < ? d s2502 t rdv = 15 ? s t su < 1 ? s
ds2502 program pulse timing diagram figure 12 20 of 23
ds2502 21 of 23 absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +12.0v operating temperature -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper ation sections of th is specification is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 6 logic 0 v il -0.3 +0.8 v 1, 11 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 ? a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v valid eprom read voltage v epr 2.8 6.0 v 13 capacitance (t a =25c) parameter symbol min typ max units notes data (1-wire) c in/out 800 pf 9 ac electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s write 0 low time t low0 60 120 s read data valid t rdv exactly 15 s release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 reset time low t rstl 480 960 s 14 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s delay to program t dp 5 ? s 10 delay to verify t dv 5 s 10 program pulse width t pp 480 5000 s 10, 12 program voltage rise time t rp 0.5 5.0 s 10 program voltage fall time t fp 0.5 5.0 s 10
ds2502 22 of 23 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence ca nnot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 ? s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1-wire bus.) 6. v ih is a function of the external pullup resistor and the pull-up voltage. 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5 k? pullup to v cc and a maximum time slot of 120 s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? resistor is used to pullup the data line to v cc , 5 s after power has been applied the parasite capacitance will not affect normal communications. 10. maximum 1-wire voltage for programming parameters is 11.5v to 12.0v; temp erature range is -40c to +50c. 11. under certain low-voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 12. the accumulative duration of the programming pulse s for each address must not exceed 5 ms. 13. ic operation and 1-wire communication is valid at v pup =2.5v or higher, but eprom data read is only valid when v pup =2.8v or higher. 14. reset low pulse on dq must be preceded by a valid t rec recovery time above the minimum v pup voltage of 2.5v.
ds2502 23 of 23 revision history revision date description pages changed added note to figure 10 that changed t rstl to 960 ? s maximum. 18 added vepr specification. changed t rstl to 960 ? s maximum. 21 12/09 added notes 13 and 14. 22

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